Semiconductor-On-Insulator (SOI) wafers, which may be formed from a handle wafer and a donor wafer, have received considerable interest in the art, due to the advantageous properties arising from the presence of a dielectric layer disposed beneath the device layer in these structures. In many applications, as in the fabrication of MOSFETs, the use of SOI wafers offers several advantageous properties in the resulting device, such as reduced leakage currents and lower capacitance.
The properties of devices fabricated on SOI wafers may be further enhanced by the application of strain across the device layer or portions thereof. For example, in MOSFET devices built on SOI wafers, the application of tensile strain across the channel layer of these devices is found to enhance carrier mobility in the PMOS regions of the device. Hence, strained SOI structures (often referred to as SSOI structures) combine the benefits of SOI technology with those of strained semiconductor technology.